HARDWARE DESCRIPTION LANGUAGES
Academic year and teacher
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- Versione italiana
- Academic year
- 2015/2016
- Teacher
- MICHELE FAVALLI
- Credits
- 6
- Didactic period
- Primo Semestre
- SSD
- ING-INF/05
Training objectives
- The course provides some basic concept in design automation and verification of digital systems
Knowledge
Basics of digital systems' design and simulation based verification at different logic levels. The role of design automation tools. Syntax and semantic of the hardware description language VHDL. Performance of digital systems. High-level synthesis and optimization of digital systems.
Capability
Capability to write VHDL models of medium sized digital blocks described at different abstraction levels (gate, RTL, architecture).
Capability to verify such models by using logic level simulation.
Capability to analyze simple high-levels algorithms and to synthesize and optimize them. Prerequisites
- Basic knowledge of digital modules and switching theory. Basic concepts of programing languages. Elementary concepts of computer architecture.
Course programme
- Introduction to digital systems design and verification:
Description levels
Logic synthesis and verification
The VHDL language
syntax and semantic
the VHDL role in simulation and synthesis
modeling and synthesis of digital modules
Digital systems performance
metric (cost, throughput and latency)
clock frequency constraints
static timng analysis
performance improvement: architectural and gate level techniques
High-level synthesis
Data Flow Graph and Control Flow Graph extraction from high-level algorithm descriptions
allocation and scheduling
scheduling algorithms for design optimization
Introduction to FPGA technologies Didactic methods
- The course consists of frontal lessons and laboratory exercises with the use of design automation tools.
Learning assessment procedures
- The exam is divided in 3 parts:
a brief report on the laboratory activities (0-3 points) is required to verify the understanding of such exercises;
a written partial exam with simple exercises regarding either the course theory or the modeling and optimization of small digital modules (0-15 points);
a project whose theme is assigned by the teacher (0-15 points). Each project requires the understanding of one of course topics, its and its application to a specific design or verification problem,
The exam outcome is positive if the student achieves at least 9 points in the written exam and 9 points in the project. Reference texts
- Handouts provided by the teacher and available on the course website.
Suggested textbook as a refernce for VHDL language:
Zwolinski M. , VHDL - digital systems design, Pearson - Prentice-Hall
